363 search results - page 55 / 73 » FPGA interconnect design using logical effort |
MICRO
2003
IEEE
14 years 25 days ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...