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» FPGA interconnect design using logical effort
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FCCM
2002
IEEE
156views VLSI» more  FCCM 2002»
14 years 14 days ago
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...
SERP
2003
13 years 9 months ago
A Software Library for SyncML Server Applications
The SyncML, the standard synchronization protocol, supports the synchronization of various application services such as an address book, a calendar. Even with this standard protoc...
JiYeon Lee, Hoon Choi
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 4 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 4 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DAC
2008
ACM
14 years 8 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...