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ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 4 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
14 years 18 days ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...
ISPASS
2009
IEEE
14 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
TOG
2010
157views more  TOG 2010»
13 years 2 months ago
Combining global and local virtual lights for detailed glossy illumination
Accurately rendering glossy materials in design applications, where previewing and interactivity are important, remains a major challenge. While many fast global illumination solu...
Tomás Davidovic, Jaroslav Krivánek, ...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 4 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran