Abstract--The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to pow...
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
Yungseon Eo, Seongkyun Shin, William R. Eisenstadt...
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...