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DAC
2004
ACM
14 years 11 months ago
Efficient on-line testing of FPGAs with provable diagnosabilities
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
Vinay Verma, Shantanu Dutt, Vishal Suthar
TCAD
2002
146views more  TCAD 2002»
13 years 10 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
14 years 4 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
14 years 4 months ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
14 years 4 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi