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VLSID
2002
IEEE
126views VLSI» more  VLSID 2002»
14 years 8 months ago
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
Debashis Panigrahi, Clark N. Taylor, Sujit Dey
IPPS
2005
IEEE
14 years 1 months ago
A Hardware Acceleration Unit for MPI Queue Processing
With the heavy reliance of modern scientific applications upon the MPI Standard, it has become critical for the implementation of MPI to be as capable and as fast as possible. Th...
Keith D. Underwood, K. Scott Hemmert, Arun Rodrigu...
ICRA
2010
IEEE
189views Robotics» more  ICRA 2010»
13 years 6 months ago
Affordable SLAM through the co-design of hardware and methodology
— Simultaneous localization and mapping (SLAM) is a prominent feature for autonomous robots operating in undefined environments. Applications areas such as consumer robotics app...
Stéphane Magnenat, Valentin Longchamp, Mich...
DSD
2007
IEEE
133views Hardware» more  DSD 2007»
14 years 2 months ago
A Serial Logarithmic Number System ALU
Serial arithmetic uses less hardware than parallel arithmetic. Serial floating point (FP) is slower than parallel FP. The Logarithmic Number System (LNS) simplifies operations, ...
Mark G. Arnold, Panagiotis D. Vouzis
FPL
2003
Springer
91views Hardware» more  FPL 2003»
14 years 27 days ago
FPGA Implementation of a Maze Routing Accelerator
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...
John A. Nestor