522 search results - page 75 / 105 » Fast Smith-Waterman hardware implementation |
ARITH
2009
IEEE
14 years 2 months ago
2009
IEEE
—The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advan...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric...
VLSISP
2008
13 years 7 months ago
2008
This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract 2nd -order statistical features from video frames. These features ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
ARITH
1999
IEEE
14 years 1 days ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...