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DAC
2010
ACM
13 years 5 months ago
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li
INFOCOM
2009
IEEE
14 years 2 months ago
Robust Counting Via Counter Braids: An Error-Resilient Network Measurement Architecture
—A novel counter architecture, called Counter Braids, has recently been proposed for accurate per-flow measurement on high-speed links. Inspired by sparse random graph codes, Co...
Yi Lu, Balaji Prabhakar
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 11 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
POPL
2003
ACM
14 years 7 months ago
Bitwidth aware global register allocation
Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a r...
Sriraman Tallam, Rajiv Gupta
EWSN
2009
Springer
14 years 2 months ago
SCOPES: Smart Cameras Object Position Estimation System
In this paper we present SCOPES, a distributed Smart Camera Object Position Estimation sensor network System that provides maps of distribution of people in indoors environments. ...
Ankur Kamthe, Lun Jiang, Matthew Dudys, Alberto Ce...