Sciweavers

281 search results - page 53 / 57
» Fastpath Speculative Parallelization
Sort
View
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
14 years 4 months ago
Data-Dependency Graph Transformations for Superblock Scheduling
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
IEEEPACT
2005
IEEE
14 years 3 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 3 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
ICS
2004
Tsinghua U.
14 years 3 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
ISCA
2010
IEEE
189views Hardware» more  ISCA 2010»
14 years 3 months ago
RETCON: transactional repair without replay
Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the se...
Colin Blundell, Arun Raghavan, Milo M. K. Martin