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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 4 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
ISSRE
2002
IEEE
14 years 2 months ago
A Case Study Using the Round-Trip Strategy for State-Based Class Testing
A number of strategies have been proposed for state-based class testing. An important proposal was made by Chow [5] and adapted by Binder [3]: It consists in deriving test sequenc...
Giuliano Antoniol, Lionel C. Briand, Massimiliano ...
ETS
2010
IEEE
153views Hardware» more  ETS 2010»
13 years 8 months ago
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
ÑIn this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analy...
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio,...
FTCS
1997
100views more  FTCS 1997»
13 years 11 months ago
Discriminating Fault Rate and Persistency to Improve Fault Treatment
In this paper the consolidate identification of faults, distinguished as transient or permanent/intermittent, is approached. Transient faults discrimination has long been performe...
Andrea Bondavalli, Silvano Chiaradonna, Felicita D...
FPL
2004
Springer
94views Hardware» more  FPL 2004»
14 years 3 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...