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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
SP
2010
IEEE
158views Security Privacy» more  SP 2010»
13 years 11 months ago
Tamper Evident Microprocessors
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...
Adam Waksman, Simha Sethumadhavan
MICRO
2009
IEEE
507views Hardware» more  MICRO 2009»
14 years 2 months ago
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure on...
Moinuddin K. Qureshi, John Karidis, Michele France...
IPPS
2006
IEEE
14 years 1 months ago
Improving cooperation in peer-to-peer systems using social networks
Rational and selfish nodes in P2P systems usually lack effective incentives to cooperate, contributing to the increase of free-riders, and degrading the system performance. Variou...
Wenyu Wang, Li Zhao, Ruixi Yuan
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
14 years 1 months ago
An Asynchronous PLA with Improved Security Characteristics
Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. T...
Petros Oikonomakos, Simon W. Moore