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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 1 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
ASAP
2008
IEEE
145views Hardware» more  ASAP 2008»
14 years 2 months ago
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yass...
DSD
2010
IEEE
190views Hardware» more  DSD 2010»
13 years 8 months ago
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
I. Sajid, Sotirios G. Ziavras, M. M. Ahmed
SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
14 years 1 months ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
14 years 1 months ago
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys
MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A...
Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nad...