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» Fault Tolerance for Multistage Interconnection Networks
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DAC
2003
ACM
14 years 8 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
SNPD
2007
13 years 9 months ago
Biswapped Networks and Their Topological Properties
In this paper, we propose a new class of interconnection networks, called “biswapped networks” (BSNs). Each BSN is built of 2n copies of some n-node basis network using a simp...
Wenjun Xiao, Weidong Chen, Mingxin He, Wenhong Wei...
DAC
2011
ACM
12 years 7 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
DAC
2006
ACM
13 years 11 months ago
Steiner network construction for timing critical nets
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
GECCO
2008
Springer
161views Optimization» more  GECCO 2008»
13 years 9 months ago
An evolutionary design technique for collective communications on optimal diameter-degree networks
Scheduling collective communications (CC) in networks based on optimal graphs and digraphs has been done with the use of the evolutionary techniques. Inter-node communication patt...
Jirí Jaros, Vaclav Dvorak