47 search results - page 2 / 10 » Fault Tolerant System Design Method Based on Self-Checking C... |
DFT
2003
IEEE
14 years 21 days ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
ATAL
2009
Springer
14 years 2 months ago
2009
Springer
The ability to guarantee that a system will continue to operate correctly under degraded conditions is key to the success of adopting multi-agent systems (MAS) as a paradigm for d...
CAMP
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...