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» Fault simulation on reconfigurable hardware
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DSN
2003
IEEE
14 years 2 months ago
Integrating Recovery Strategies into a Primary Substation Automation System
The DepAuDE architecture provides middleware to integrate fault tolerance support into distributed embedded automation applications. It allows error recovery to be expressed in te...
Geert Deconinck, Vincenzo De Florio, Ronnie Belman...
ISCA
2005
IEEE
79views Hardware» more  ISCA 2005»
14 years 2 months ago
Design and Evaluation of Hybrid Fault-Detection Systems
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
CODES
2003
IEEE
14 years 2 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
14 years 1 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
14 years 6 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...