372 search results - page 64 / 75 » Fault simulation on reconfigurable hardware |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
VTS
2002
IEEE
14 years 25 days ago
2002
IEEE
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...