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» Fault simulation on reconfigurable hardware
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DFT
2005
IEEE
81views VLSI» more  DFT 2005»
14 years 1 months ago
Modeling QCA Defects at Molecular-level in Combinational Circuits
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
14 years 26 days ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ICCAD
2002
IEEE
161views Hardware» more  ICCAD 2002»
14 years 4 months ago
Non-tree routing for reliability and yield improvement
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 7 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
12 years 11 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...