Sciweavers

75 search results - page 8 / 15
» Fault tolerant methods for reliability in FPGAs
Sort
View
DAC
2002
ACM
14 years 10 months ago
Software-based diagnosis for processors
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnos...
Li Chen, Sujit Dey
DATE
2009
IEEE
73views Hardware» more  DATE 2009»
14 years 4 months ago
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs
—Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are al...
Francesco Abate, Luca Sterpone, Massimo Violante, ...
IJNSEC
2008
126views more  IJNSEC 2008»
13 years 9 months ago
A Hybrid Group Key Management Protocol for Reliable and Authenticated Rekeying
We present a hybrid group key management protocol that incorporates both a centralized and a contributory scheme for key management, and a tree-based Elliptic Curve Diffie-Hellman...
Depeng Li, Srinivas Sampalli
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 3 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
ICPP
2007
IEEE
14 years 4 months ago
Fault-Driven Re-Scheduling For Improving System-level Fault Resilience
The productivity of HPC system is determined not only by their performance, but also by their reliability. The conventional method to limit the impact of failures is checkpointing...
Yawei Li, Prashasta Gujrati, Zhiling Lan, Xian-He ...