229 search results - page 22 / 46 » Fault-Tolerant Clock Synchronization in CAN |
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
ISPD
2004
ACM
14 years 1 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the tim...
ASYNC
2003
IEEE
14 years 1 months ago
2003
IEEE
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...
CNSR
2010
IEEE
13 years 11 months ago
2010
IEEE
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...