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ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
14 years 4 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
ISPD
2000
ACM
124views Hardware» more  ISPD 2000»
13 years 12 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Masanori Hashimoto, Hidetoshi Onodera
ISQED
2003
IEEE
116views Hardware» more  ISQED 2003»
14 years 26 days ago
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper prop...
Tom Chen, Amjad Hajjar
WSC
2008
13 years 10 months ago
Reliable simulation with input uncertainties using an interval-based approach
Uncertainty associated with input parameters and models in simulation has gained attentions in recent years. The sources of uncertainties include lack of data and lack of knowledg...
Ola Ghazi Batarseh, Yan Wang
AIPS
2008
13 years 10 months ago
Generating Robust Schedules Subject to Resource and Duration Uncertainties
We consider the Resource-Constrained Project Scheduling Problem with minimal and maximal time lags under resource and duration uncertainties. To manage resource uncertainties, we ...
Na Fu, Hoong Chuin Lau, Fei Xiao