172 search results - page 11 / 35 » FinFET-based SRAM design |
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
TON
2008
13 years 7 months ago
2008
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...