Sciweavers

172 search results - page 12 / 35
» FinFET-based SRAM design
Sort
View
ICCAD
2004
IEEE
85views Hardware» more  ICCAD 2004»
14 years 4 months ago
Improving soft-error tolerance of FPGA configuration bits
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 18 days ago
An RDL-configurable 3D memory tier to replace on-chip SRAM
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
Marco Facchini, Paul Marchal, Francky Catthoor, Wi...
SIGCOMM
2000
ACM
13 years 11 months ago
Memory-efficient state lookups with fast updates
Routers must do a best matching pre x lookup for every packet solutions for Gigabit speeds are well known. As Internet link speeds higher, we seek a scalable solution whose speed ...
Sandeep Sikka, George Varghese
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
13 years 11 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
14 years 4 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood