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ISCAS
2003
IEEE
124views Hardware» more  ISCAS 2003»
14 years 23 days ago
An active leakage-injection scheme applied to low-voltage SRAMs
ABSTRACT: An active leakage-injection scheme (ALIS) for lowvoltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a commond...
Jader A. De Lima
VLSID
2009
IEEE
220views VLSI» more  VLSID 2009»
14 years 8 months ago
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (Q...
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic march tests generations for static linked faults in SRAMs
Static Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and m...
Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Gi...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 4 months ago
Breaking the simulation barrier: SRAM evaluation through norm minimization
— With process variation becoming a growing concern in deep submicron technologies, the ability to efficiently obtain an accurate estimate of failure probability of SRAM compone...
Lara Dolecek, Masood Qazi, Devavrat Shah, Anantha ...
SOCC
2008
IEEE
151views Education» more  SOCC 2008»
14 years 1 months ago
Failure analysis for ultra low power nano-CMOS SRAM under process variations
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...