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MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
14 years 1 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
IOLTS
2005
IEEE
163views Hardware» more  IOLTS 2005»
14 years 1 months ago
Modeling Soft-Error Susceptibility for IP Blocks
As device geometries continue to shrink, single event upsets are becoming of concern to a wider spectrum of system designers. These “soft errors” can be a nuisance or catastro...
Robert C. Aitken, Betina Hold
ANCS
2005
ACM
14 years 1 months ago
Fast and scalable pattern matching for content filtering
High-speed packet content inspection and filtering devices rely on a fast multi-pattern matching algorithm which is used to detect predefined keywords or signatures in the packe...
Sarang Dharmapurikar, John W. Lockwood
SIGCOMM
2004
ACM
14 years 26 days ago
Sizing router buffers
All Internet routers contain buffers to hold packets during times of congestion. Today, the size of the buffers is determined by the dynamics of TCP’s congestion control algor...
Guido Appenzeller, Isaac Keslassy, Nick McKeown
ITC
2003
IEEE
168views Hardware» more  ITC 2003»
14 years 22 days ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...