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» FinFET-based SRAM design
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ISPD
2012
ACM
248views Hardware» more  ISPD 2012»
12 years 3 months ago
A fast estimation of SRAM failure rate using probability collectives
Importance sampling is a popular approach to estimate rare event failures of SRAM cells. We propose to improve importance sampling by probability collectives. First, we use “Kul...
Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei ...
VLSI
2005
Springer
14 years 1 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
13 years 5 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...
ICCAD
2010
IEEE
133views Hardware» more  ICCAD 2010»
13 years 4 months ago
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia...
JCP
2008
232views more  JCP 2008»
13 years 7 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...