23 search results - page 3 / 5 » Finite state machine state assignment for area and power min... |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ICTAI
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a Finite State Machine is modifie...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...