Sciweavers

69 search results - page 6 / 14
» First Order Decision Diagrams for Relational MDPs
Sort
View
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
14 years 11 days ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu
GLVLSI
1996
IEEE
145views VLSI» more  GLVLSI 1996»
13 years 11 months ago
Boolean Function Representation Using Parallel-Access Diagrams
Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...
Valeria Bertacco, Maurizio Damiani
ICDE
2007
IEEE
145views Database» more  ICDE 2007»
14 years 8 months ago
Fast Identification of Relational Constraint Violations
Logical constraints, (e.g., 'phone numbers in toronto can have prefixes 416, 647, 905 only'), are ubiquitous in relational databases. Traditional integrity constraints, ...
Amit Chandel, Nick Koudas, Ken Q. Pu, Divesh Sriva...
ICCD
2001
IEEE
176views Hardware» more  ICCD 2001»
14 years 4 months ago
BDD Variable Ordering by Scatter Search
Reduced Ordered Binary Decision Diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions which are frequently used in VLSI Design Automation. ...
William N. N. Hung, Xiaoyu Song
ATVA
2006
Springer
100views Hardware» more  ATVA 2006»
13 years 11 months ago
A Fine-Grained Fullness-Guided Chaining Heuristic for Symbolic Reachability Analysis
Chaining can reduce the number of iterations required for symbolic state-space generation and model-checking, especially in Petri nets and similar asynchronous systems, but require...
Ming-Ying Chung, Gianfranco Ciardo, Andy Jinqing Y...