107 search results - page 14 / 22 » Fixed-Polynomial Size Circuit Bounds |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
ATS
2005
IEEE
13 years 9 months ago
2005
IEEE
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
ISPD
2000
ACM
14 years 1 days ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
PODC
2009
ACM
14 years 8 months ago
2009
ACM
A method is given for constructing a max register, a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the larges...