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» Fixed-Polynomial Size Circuit Bounds
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VTS
2007
IEEE
135views Hardware» more  VTS 2007»
14 years 1 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
DAGSTUHL
2006
13 years 9 months ago
The optimal sequence compression
This paper presents the optimal compression for sequences with undefined values. Let we have (N -m) undefined and m defined positions in the boolean sequence V of length N. The se...
Alexander E. Andreev
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
13 years 5 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
TIT
2008
116views more  TIT 2008»
13 years 7 months ago
On the Complexity of Hardness Amplification
We study the task of transforming a hard function f, with which any small circuit disagrees on (1 - )/2 fraction of the input, into a harder function f , with which any small circ...
Chi-Jen Lu, Shi-Chun Tsai, Hsin-Lung Wu
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
14 years 2 months ago
Multi-Vector Tests: A Path to Perfect Error-Rate Testing
The importance of testing approaches that exploit error tolerance to improve yield has previously been established. Error rate, defined as the percentage of vectors for which the...
Shideh Shahidi, Sandeep Gupta