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    ISLPED
    1996
    ACM
    143views Hardware» more  ISLPED 1996»
    Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
    14 years 2 months ago
    Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
    Download  www.cecs.uci.edu
    Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Ko...
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    CHES
    2006
    Springer
    87views Cryptology» more  CHES 2006»
    Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
    14 years 1 months ago
    Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
    Download  www.iacr.org
    Stefan Tillich, Johann Großschädl
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    DAC
    2008
    ACM
    112views Computer Architecture» more  DAC 2008»
    IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
    13 years 11 months ago
    IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
    Download  www.stanford.edu
    Sung-Boem Park, Subhasish Mitra
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    DAGSTUHL
    2007
    69views Software Engineering» more  DAGSTUHL 2007»
    Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors
    13 years 11 months ago
    Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors
    Download  www.dagstuhl.de
    Manuel Wendt, Matthias Grumer, Christian Steger, U...
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    JSA
    2008
    63views more  JSA 2008»
    DLL-conscious instruction fetch optimization for SMT processors
    13 years 9 months ago
    DLL-conscious instruction fetch optimization for SMT processors
    Download  arch.ece.gatech.edu
    Fayez Mohamood, Mrinmoy Ghosh, Hsien-Hsin S. Lee
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