Sciweavers

1563 search results - page 37 / 313
» Flexible instruction processors
Sort
View
ARCS
1997
Springer
14 years 2 months ago
A RISC Processor with Extended Forwarding
The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by...
Gert Markwardt, Günter Kemnitz, Rainer G. Spa...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 2 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 4 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
14 years 2 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
ASPLOS
1987
ACM
14 years 1 months ago
Pipelining and Performance in the VAX 8800 Processor
The VAX 8800 family (models 8800, 8700, 8550), currently the fastest computers in the VAX product line, achieve their speed through a combination of fast cycle time and deep pipel...
Douglas W. Clark