1563 search results - page 38 / 313 » Flexible instruction processors |
ICCAD
2003
IEEE
14 years 6 months ago
2003
IEEE
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
CODES
2005
IEEE
14 years 3 months ago
2005
IEEE
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
HPCA
2004
IEEE
14 years 10 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
Code size and energy consumption are critical design concerns for embedded processors as they determine the cost of the overall system. Techniques such as reduced length instructi...
ASPDAC
2005
ACM
13 years 12 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...