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DAC
2008
ACM
14 years 9 months ago
Run-time instruction set selection in a transmutable embedded processor
We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run...
Jörg Henkel, Lars Bauer, Muhammad Shafique
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
14 years 2 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
14 years 2 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
CASES
2008
ACM
13 years 10 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou