1563 search results - page 46 / 313 » Flexible instruction processors |
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
AES
2000
Springer
14 years 2 months ago
2000
Springer
We present a method for finding efficient instruction sequences for the Serpent S-boxes. Current implementations need many registers to store temporary variables, yet the common ...
CODES
2001
IEEE
14 years 1 months ago
2001
IEEE
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
APCSAC
2001
IEEE
14 years 1 months ago
2001
IEEE
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...