1563 search results - page 61 / 313 » Flexible instruction processors |
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
Runahead execution improves memory latency tolerance without significantly increasing processor complexity. Unfortunately, a runahead execution processor executes significantly mo...
LCPC
2004
Springer
14 years 3 months ago
2004
Springer
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
ICCD
2001
IEEE
14 years 6 months ago
2001
IEEE
General-purpose microprocessors augmented with SIMD execution units enhance multimedia applications by exploiting data level parallelism. However, supporting/overhead related inst...
ICCAD
1997
IEEE
14 years 2 months ago
1997
IEEE
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...