1563 search results - page 63 / 313 » Flexible instruction processors |
ISCA
2003
IEEE
14 years 3 months ago
2003
IEEE
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
DAC
2007
ACM
14 years 11 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
MICRO
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
ASYNC
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...
CODES
2008
IEEE
14 years 4 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...