1563 search results - page 71 / 313 » Flexible instruction processors |
ICCD
2001
IEEE
14 years 8 months ago
2001
IEEE
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permut...
ISPASS
2007
IEEE
14 years 5 months ago
2007
IEEE
For simulation, a tradeoff exists between speed and accuracy. The more instructions simulated from the workload, the more accurate the results — but at a higher cost. To reduce ...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
MICRO
1991
IEEE
14 years 2 months ago
1991
IEEE
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...