43 search results - page 5 / 9 » Floorplan area minimization using Lagrangian relaxation |
TIP
1998
13 years 7 months ago
1998
Abstract—In this paper, we propose an optimal quadtree (QT)based motion estimator for video compression. It is optimal in the sense that for a given bit budget for encoding the d...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
IEEEMSP
2002
IEEE
14 years 14 days ago
2002
IEEE
—This paper presents an operational rate-distortion (ORD) optimal approach for skeleton-based boundary encoding. The boundary information is first decomposed into skeleton and di...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...