161 search results - page 25 / 33 » Floorplanning with Datapath Optimization |
ICCD
2004
IEEE
14 years 7 months ago
2004
IEEE
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ISCAS
2005
IEEE
14 years 4 months ago
2005
IEEE
In high-level synthesis, accurate lower-bound estimation is helpful to explore the search space efficiently and to evaluate the quality of heuristic algorithms. For the lower-bound...
DAC
1996
ACM
14 years 3 months ago
1996
ACM
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
ASPDAC
1995
ACM
14 years 2 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...