Sciweavers

578 search results - page 94 / 116
» Flow Map Layout
Sort
View
DAC
2004
ACM
16 years 4 months ago
Efficient power/ground network analysis for power integrity-driven design methodology
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
Su-Wei Wu, Yao-Wen Chang
155
Voted
DAC
2006
ACM
16 years 4 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
ICFP
2001
ACM
16 years 3 months ago
Functioning without Closure: Type-Safe Customized Function Representations for Standard ML
The CIL compiler for core Standard ML compiles whole ML programs using a novel typed intermediate language that supports the generation of type-safe customized data representation...
Allyn Dimock, Ian Westmacott, Robert Muller, Frank...
119
Voted
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
16 years 20 days ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
IPPS
2009
IEEE
15 years 10 months ago
High-order stencil computations on multicore clusters
Stencil computation (SC) is of critical importance for broad scientific and engineering applications. However, it is a challenge to optimize complex, highorder SC on emerging clus...
Liu Peng, Richard Seymour, Ken-ichi Nomura, Rajiv ...