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ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
14 years 18 days ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
IJIT
2004
13 years 9 months ago
Formal Verification of a Multicast Protocol In Mobile Networks
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
Mohammad Reza Matash Borujerdi, S. M. Mirzababaei
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 5 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
DAC
2002
ACM
14 years 9 months ago
High-Level specification and automatic generation of IP interface monitors
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
Marcio T. Oliveira, Alan J. Hu
IEEESCC
2005
IEEE
14 years 2 months ago
Using a Rigorous Approach for Engineering Web Service Compositions: A Case Study
In this paper we discuss a case study for the UK Police IT Organisation (PITO) on using a model-based approach to verifying web service composition interactions for a coordinated ...
Howard Foster, Sebastián Uchitel, Jeff Mage...