726 search results - page 6 / 146 » Formal Verification and Validation of Interactive Systems Sp... |
ASYNC
2007
IEEE
14 years 13 days ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
HVC
2007
Springer
14 years 9 days ago
2007
Springer
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
RSP
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process f...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
CCECE
2006
IEEE
14 years 2 months ago
2006
IEEE
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...