216 search results - page 16 / 44 » Formal Verification of Safety Properties in Timed Circuits |
ASIAN
2009
Springer
13 years 8 months ago
2009
Springer
Abstract. Clever algorithm design is sometimes superseded by simple encodings into logic. We apply this motto to a few case studies in the formal verification of security propertie...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
FORMATS
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Quantitative verification techniques are able to establish system properties such as "the probability of an airbag failing to deploy on demand" or "the exp...
EMSOFT
2006
Springer
13 years 9 months ago
2006
Springer
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...