1446 search results - page 136 / 290 » Formal analysis of hardware requirements |
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...
ASPDAC
2001
ACM
14 years 2 months ago
2001
ACM
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...
ASPDAC
2012
ACM
12 years 6 months ago
2012
ACM
—In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the beh...
CAV
2012
Springer
12 years 1 months ago
2012
Springer
We present Joogie, a tool that detects infeasible code in Java programs. Infeasible code is code that does not occur on feasible controlflow paths and thus has no feasible executi...
ISCAS
2002
IEEE
14 years 3 months ago
2002
IEEE
Due to technology limitations as well as stringent operating conditions that are imposed, the design of fully integrated analog RF front-end circuits is aimed at the edge of the r...