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» Formal analysis of hardware requirements
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MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
14 years 2 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
14 years 1 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
12 years 11 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
ASAP
2011
IEEE
233views Hardware» more  ASAP 2011»
12 years 8 months ago
Accelerating vision and navigation applications on a customizable platform
—The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computati...
Jason Cong, Beayna Grigorian, Glenn Reinman, Marco...
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
14 years 2 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic