34 search results - page 3 / 7 » Formal hardware verification by integrating HOL and MDG |
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
ACSD
2001
IEEE
13 years 11 months ago
2001
IEEE
We present a new way to define the semantics of imperative synchronous languages by means of separating the control and the data flow. The control flow is defined by predicates th...
TAP
2008
Springer
13 years 7 months ago
2008
Springer
Formal methods can only gain widespread use in industrial software development if they are integrated into software development techniques, tools, and languages used in practice. A...
DATE
2010
IEEE
13 years 12 months ago
2010
IEEE
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...