53 search results - page 6 / 11 » From Equation to VHDL: Using Rewriting Logic for Automated F... |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
ENTCS
2006
13 years 7 months ago
2006
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
FLOPS
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. We present a practical tool for defining and proving properties of recursive functions in the Coq proof assistant. The tool generates from pseudo-code the graph of the in...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...