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DATE
2008
IEEE
75views Hardware» more  DATE 2008»
14 years 1 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
Debasish Das, Kip Killpack, Chandramouli V. Kashya...
ETFA
2005
IEEE
14 years 29 days ago
Assessment of PROFIBUS networks using a fault injection framework
Industrial control systems architectures have been evolving to the decentralization of control tasks. This evolution associated with the time-critical nature of these tasks, incre...
J. A. Carvalho, A. S. Carvalho, Paulo Portugal
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 19 days ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
TODAES
2002
134views more  TODAES 2002»
13 years 7 months ago
False-noise analysis using logic implications
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...