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» From single to multiprocessor real-time kernels in hardware
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CACM
2010
179views more  CACM 2010»
13 years 8 months ago
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating syste...
Peter Sewell, Susmit Sarkar, Scott Owens, Francesc...
IEEEPACT
2006
IEEE
14 years 2 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
CODES
2003
IEEE
14 years 1 months ago
Deriving process networks from weakly dynamic applications in system-level design
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
Todor Stefanov, Ed F. Deprettere
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
14 years 28 days ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
PAM
2007
Springer
14 years 2 months ago
Packet Capture in 10-Gigabit Ethernet Environments Using Contemporary Commodity Hardware
Abstract. Tracing traffic using commodity hardware in contemporary highspeed access or aggregation networks such as 10-Gigabit Ethernet is an increasingly common yet challenging t...
Fabian Schneider, Jörg Wallerich, Anja Feldma...