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ICASSP
2011
IEEE
12 years 11 months ago
A distance-based slice interleaving scheme for robust video transmission over error-prone networks
Video transmission over wireless networks suffers from packet loss due to either temporary packet drop or fadinginduced bit errors. To ensure that the quality of the decoded video...
Yu Wang, Jo Yew Tham, Kwong Huang Goh, Wei Siong L...
DT
2000
162views more  DT 2000»
13 years 7 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 5 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
ICCAD
2003
IEEE
117views Hardware» more  ICCAD 2003»
14 years 4 months ago
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
14 years 2 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...